An embodiment of the present invention relates to the field of electronic systems and, more particularly, to a method and apparatus for controlling power management state transitions, and, in particular, transitions into and out of a deeper sleep state, for example.
Power consumption continues to be an important issue for many current computing system including personal computers, wireless handsets, personal digital assistants, etc.
In today's mobile computing environment, for example, to address power dissipation concerns, certain components may be placed into lower power states based on reduced activity or demand. For one approach, an operating system may support a built-in power management software interface such as Advanced Configuration and Power Interface (ACPI). ACPI describes a power management policy including various “C states” that may be supported by processors and/or chipsets. For this policy, C0 is defined as the Run Time state in which the processor operates at high voltage and high frequency. C1 is defined as the Auto HALT state in which the core clock is stopped internally. C2 is defined as the Stop Clock state in which the core clock is stopped externally. C3 is defined as the Deep Sleep state in which all processor clocks are shut down, and C4 is defined as the Deeper Sleep state in which all processor clocks are stopped and the processor voltage is reduced to a lower data retention point. Of the various C states, C4 or Deeper Sleep, is the lowest power state.
In operation, to enter the Deeper Sleep state, ACPI may detect a time slot in which there are no new or pending interrupts to the mobile processor. The ACPI policy then uses input/output (I/O) controller or other chipset features to place the mobile processor into the Deeper Sleep state.
Once the processor is placed into this C4 state, a break event or interrupt from the operating system or another source may be sent to the chipset, and the chipset will then allow the processor to exit the Deeper Sleep state. The ability to transition between various power management states, including the Deeper Sleep state, may enable power dissipation to be reduced and battery life to be increased.
Currently, entry into Deeper Sleep is done by referencing an external voltage reference in the processor voltage regulator circuit and regulating to this reference voltage whenever a platform “Deeper Sleep” signal such as a DPRSLPVR signal or other similar signal is asserted by the I/O controller or other integrated circuit. The voltage regulator then transitions from a first voltage to a second lower voltage associated with the Deeper Sleep state. Upon exiting the Deeper Sleep state, a voltage transition in the other direction takes place with a similar specified time window. Using current approaches, Deeper Sleep entry and exit latency times may be relatively large and may lead to system performance degradation and/or reduce potential power savings.
In some cases, the Deeper Sleep entry/exit latencies may further prevent some systems from ever entering the Deeper Sleep state. For example, systems that include an active Universal Serial Bus 1 (USB1) and/or AC'97 (Audio Codec '97) device may have difficulty entering the C4 power state because the operating system may not tolerate the long latency associated with transitioning out of C4 and back to C0 to handle a USB1 interrupt. Where there is a concern that interrupts may be lost due to this latency, a processor may be prevented from entering the C4 state altogether. The result may be an increase in the processor average power dissipation and a reduction in battery life versus systems that are able to enter C4.